Gettering and defect engineering in semiconductor technology XVI: Selected, peer reviewed papers from the GADEST 2015: Gettering and Defect Engineering in Semiconductor Technology, September 20-25, 2015, Bad Staffelstein, Germany Pichler, Peter (Hrsg.) … Hierarchical variability-aware compact models of 20nm bulk CMOS Wang, Xingsheng; Reid, D.; Wang, Liping; Burenkov, A.; Millar, C.; Lorenz, J.; Asenov, A … Numerical evaluation of the ITRS transistor scaling Nagy, R.; Burenkov, A.; Lorenz, J … Simulation of plasma immersion ion implantation into silicon Burenkov, A.; Lorenz, J.; Spiegel, Y.; Torregrosa, F … Advanced extra functionality CMOS-based devices Cristiano, F.; Pichler, P.; Tavernier, C.; Windl, W … Challenges and opportunities for process modeling in the nanotechnology era Lorenz, JK; Baer, E.; Burenkov, A.; Erdmann, A.; Evanschitzky, P.; Pichler, P … Large boron-interstitial cluster modelling in …