In this work an integrated multi-order digital control unit (DCU), for the generation of a maximum length sequence (MLS) circulant matrix, is proposed. The system provides the binary MLS through serial output. It has the possibility to select the M order of the MLS according to the application. When compared to conventional implementations, the proposed system does not rely on read-only memory (ROM) data storage since the circulant sequences are generated on the fly during the circuit’s operation. This permits to implement multiple order circulant matrices, while mantaining a reduced area occupation. Moreover, the proposed circuit can be implemented with digital standard cell synthesis, avoiding dedicated digital flows for memories. The DCU has been verified with behavioral simulation using a 2MHz clock frequency and has been realized in CMOS $28\mathrm{~nm}$ FDSOI technology with a total area occupation of $45\mu\mathrm{m}\times 45\mu\mathrm{m}$. From the RTL synthesis, a total power consumption of $8.2\mu\mathrm{W}$ is obtained.