This paper reviews some of our achievements on the morphological and electrical properties of SiO 2/4H-SiC interfaces in 4H-SiC MOSFETs. In particular, the impact of the SiC surface morphology and of the effects of different post-oxidation-annealing (POA) of the gate oxide on the channel mobility are discussed. For this purpose, a set of standard macroscopic mobility and interface states measurements on 4H-SiC MOS-based devices processed under different conditions have been selected and correlated with a nanoscale characterization of the electrical modification induced in the SiC material by the POA. The practical implications for the devices performances are discussed.