In this paper we investigate the role of the growth rate (varied by changing the Si/H 2 ratio and using TCS to avoid Si droplet formation) on the surface roughness (R q), the density of single Shockley stacking faults (SSSF) and 3C-inclusions (ie epi-stacking faults, ESF). We find that optimized processes with higher growth rates allow to improve the films in all the considered aspects. This result, together with the reduced cost of growth processes, indicates that high growth rates should always be used to improve the overall quality of 4H-SiC homoepitaxial growths. Furthermore we analyze the connection between surface morphology and density of traps (D it) at the SiO 2/SiC interface in fabricated MOS devices finding consistent indications that higher surface roughness (step-bunched surfaces) can improve the quality of the interface by reducing the D it value.