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This work reports on the physical and electrical characterization of the oxide/semiconductor interface in MOS capacitors with the SiO 2 layer deposited by a high temperature process from dichlorosilane and nitrogen-based vapor precursors and subjected to a post deposition annealing process in N 2 O. Low interface state density (D it≈ 9.0× 10 11 cm-2 eV-1) was found at 0.2 eV from E C, which is comparable to the values typically obtained in other lower temperature deposited oxides (eg, TEOS). A barrier height of 2.8 eV was derived from the Fowler-Nordheim plot, very close to the ideal value expected for SiO 2/4H-SiC interface. Basing on these preliminary results, the integration in MOSFETs devices can be envisaged.
Trans Tech Publications Ltd
Publication date: 
1 Jan 2017

Marilena Vivona, Patrick Fiorenza, Ferdinando Iucolano, Andrea Severino, Simona Lorenti, Fabrizio Roccaforte

Biblio References: 
Volume: 897 Pages: 331-334
Materials Science Forum