The contribution addresses two needs of the current micro/nanoelectronics field: the creation of low-power consumption devices, together with the compatibility with CMOS technology. Both can be potentially fulfilled adopting single electron transistors (SETs), prepared by opportune methods, to be inserted into hybrid SET-CMOS devices.Here we focus on the electrical characterization of structures whose preparation method is suited for large-scale production of SET devices, potentially operative at room temperature: the device core is represented by few-nanometer size nanocrystals embedded in a SiO 2 matrix, and is produced by ion beam mixing and subsequent thermal annealing. The preparation starts with a Si/SiO 2/Si stack characterized by a few nm-size inner SiO 2 layer. Ion bombardment induces atom displacements between the layers, which can be partly recovered by thermal annealing. Thanks to the joint use of process simulations and experiment, it is possible to find an opportune thermal annealing process to yield few nm-size silicon crystals embedded in the middle of the SiO 2 layer. The small crystal size (< 5 nm) and the extremely narrow SiO 2 bridges (~ 2 nm) between the nanocrystals and the electrical contacts are designed to ensure high tunneling probability towards the Si quantum dot and room temperature operation. The production method should allow fast transfer to industrial processes, being scalable to standard full wafer-size processing. Results on the electrical characterization in the 5 K–350 K range of preliminary structures will be presented, in view of the realization of SET and hybrid SET-CMOS devices.