The gate oxide lifetime in 4H-SiC power MOSFETs is typically assessed at fixed and constant gate bias stress, monitoring the time-dependent dielectric breakdown (TDDB). In this work, the TDDB results obtained at three different insulator fields - either for positive and negative values - have been compared at wafer level. The TDDB was measured at 200°C under the following conditions: (i) 3 (positive or negative) gate bias values; (ii) 3 (positive or negative) gate current values; (iii) 3 different insulator fields varying the gate bias stress voltage in each device after propaedeutic capacitance measurements to determine the gate insulator thickness. The three methods gave three lifetime prediction at low oxide field (under standard device operation). The physical explanation of these findings can be found, taking into account the device design across the source-body-JFET junction and the transient trapping phenomena …