Due to the high carrier mobility, Ge and III-V semiconductors are attractive as active channels for post-Si metal oxide semiconductor (MOS) devices. However, integration of gate dielectrics on high-mobility substrates is frequently jeopardized by the electrical activity of traps nearby the interface. Active traps determination at the interface between the two semiconductors with gate dielectrics has been conducted with the aim to validate several electrical passivation methodologies. In particular, GeO2 and LaGeOx passivations of Ge ...