3C-SiC devices are hampered by a high crystal defect density due to the hetero-epitaxial growth of these films, which results in the presence of stacking faults (SF). In this paper high growth rate CVD processes have been used to try to reduce the SF density in 3C-SiC films. In a first step a high growth rate (30 μm/h) has been used to grow 50 μm thick 3C-SiC layer on (100) Si. Then the silicon substrate was removed via etching and a further 3C-SiC growth was performed with a higher growth rate (90 μm/h) at a higher temperature (1600 °C) to obtain a final thickness of 150 μm. The SF presence and density were evaluated by TEM analysis performed on as-grown samples and SEM analysis on KOH etched samples with various thicknesses. A decrease of SF density was observed with an increase of 3C-SiC film thickness, with the best results (500/cm) obtained for the thickest sample. The 3C-SiC …